Forgeby deepsilabs

Forge

The Semiconductor Testing Lifecycle Platform

Design·Test·Evaluate·Deliver

Get Started

Forge accelerates semiconductor design-testing cycles

Forge converts design documents to test code and orchestrates its execution on Automated Test Equipment (ATE).

Engineers creating silicon designs and generating documents

Ingest Design Documents

PDF, GDS, XLS — any format

Engineer and AI agent co-developing test code

AI-Assisted Test Development

Co-develop with an AI agent

Data visualizations and analysis dashboards

Analyze & Report

Visualize, flag faults, export

The Lifecycle

From silicon design to validated product

Six phases. One platform. Complete coverage of the semiconductor testing lifecycle.

Design

Engineers and researchers create silicon designs, generate layouts, and define test instructions and specifications.

Design outputs — datasheets (PDF), layout files (GDS), and specification sheets (XLS) — become the inputs for Forge.

DatasheetsLayout FilesTest SpecsWafer SpecsProduct Specs

Analyze

Forge AI agents analyze the uploaded documents, extracting critical parameters, test conditions, and device characteristics.

The agents generate preliminary detailed test case proposals, then assist with iterative refinement — referencing historical data for improved test coverage.

Document AnalysisTest Case ProposalsIterative RefinementHistorical References

Documents being funneled through AI analysis into structured test proposals

Engineer and AI brain sitting side by side co-developing test code

Co-pilot

Co-develop tests with the AI agent. Iterate over testing specifications, finalize test formats, and define expected outcomes together.

The agent writes test code and validates it with engineers — combining machine speed with human expertise.

Interactive DevelopmentSpec IterationCode ValidationEngineer Review

Orchestrate

Agents orchestrate test run cycles on Automated Test Equipment, intelligently fixing test errors and maintaining fault tolerance throughout execution.

Test measurements are captured and structured automatically. Agents also run calibration sequences for connected devices.

ATE OrchestrationError RecoveryData CaptureAuto-Calibration

AI robot operating automated test equipment with robotic arms and wafer testing

Engineer monitoring agent behavior remotely while AI operates test equipment

Observe

Observe agent behavior in real time. Engineers can monitor test execution, communicate modifications, and receive instant notifications.

Augment and adjust tests on the fly — no need to stop a run to make corrections.

Real-time MonitoringLive ModificationsNotificationsRemote Access

Evaluate

Generate rich visualizations with agent assistance — wafer maps, SPC charts, yield trends, and more.

Data is analyzed automatically to flag faults and anomalies. Export results to other surfaces for further analysis and reporting.

Auto-VisualizationFault DetectionYield AnalysisReport Export

Dashboard with charts, graphs, pie charts and exported reports

SMUVNASpectrum AnalyzerOscilloscopeDigitizerAWGParameter AnalyzerAudio AnalyzerOptical Power Meter|GPIBPXI/PXIeLXISPII2CSCPISTDF

Why Forge

Built for the way test teams actually work

IP-Safe by Design

SaaS or on-prem LLM option. Your device IP never leaves your infrastructure if you don't want it to.

Hardware-Agnostic

Runs on any bench — PXI, benchtop, or custom instrument stack. Plugs into your existing infrastructure.

Natural Language Queries

No SQL, no dashboards to learn. Ask questions about your yield data in plain English and get instant answers.

Native STDF Support

First-class STDF/ATDF ingestion. Wafer maps, SPC charts, and yield correlation out of the box.

Ready to automate your test engineering?

We're working with early design partners to build the semiconductor test platform that should have existed years ago.

Design partner slots are limited. Early partners get roadmap influence and founding pricing.

Get Started